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ADuC7060
I 2 C Master Status, I2CMSTA, Register
Name:
Address:
Default value:
Access:
Function:
I2CMSTA
0xFFFF0904
0x0000
Read only
This 16-bit MMR is the 2 C status register in master mode.
Table 95. I2CMSTA MMR Bit Designations
Bit
15 to 11
10
9
8
7
6
5
4
3
2
1 to 0
Name
I2CBBUSY
I2CMRxFO
I2CMTC
I2CMNA
I2CMBUSY
I2CAL
I2CMNA
I2CMRXQ
I2CMTXQ
I2CMTFSTA
Description
Reserved. These bits are reserved.
I 2 C bus busy status bit.
This bit is set to 1 when a start condition is detected on the I 2 C bus.
This bit is cleared when a stop condition is detected on the bus.
Master receive FIFO overflow.
This bit is set to 1 when a byte is written to the r eceive FIFO when it is already full.
This bit is cleared in all other conditions.
I 2 C transmission complete status bit.
This bit is set to 1 when a transmission is complete between the master and the slave with which it was
communicating. If the I2CMCENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
Clear this interrupt source.
I 2 C master no acknowledge data bit
This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer.
If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I 2 C master busy status bit.
Set to 1 when the master is busy processing a transaction.
Cleared if the master is ready or if another master device has control of the bus.
I 2 C arbitration lost status bit.
This bit is set to 1 when the I 2 C master did not gain control of the I 2 C bus. If the I2CALENI bit in I2CMCON is set, an
interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I 2 C master no acknowledge address bit.
This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the
I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit clears in all other conditions.
I 2 C master receive request bit.
This bit is set to 1 when data enters the ReceiveFIFO. If the I2CMRENI in I2CMCON is set, an interrupt is generated.
This bit is cleared in all other conditions.
I 2 C master transmit request bit.
This bit goes high if the transmit FIFO is empty or contains only 1 byte and the master has transmitted an address +
write. If the I2CMTENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I 2 C master transmit FIFO status bits.
00 = I 2 C master transmit FIFO empty.
01 = 1 byte in master transmit FIFO.
10 = 1 byte in master transmit FIFO.
11 = I 2 C master transmit FIFO full.
Rev. 0 | Page 84 of 100
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